EPC2LC20N-W vs EPC2CC20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20N-W sa pamamagitan ng Altera at EPC2CC20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2LC20N-W EPC2CC20N
Brand Altera Altera
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Uri ng Memory EPROM (UV-erasable, ISP) —
Laki ng Memory 1.6 Mbit —
Programmable Type In System Programmable —
Configuration Interface Serial (DATA, DCLK, OE, nCS) 16-bit parallel (FPP) / Passive Serial (PS)
Internal Oscillator Frequency 66.7 MHz —
Supply Voltage (VCC) 3.0 V to 3.6 V, 4.75 V to 5.25 V 3.3 V
ISP Interface JTAG (IEEE 1149.1) —
Supported FPGA Families APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone —
Packhaging 20-LCC (J-Lead) PLCC-20 PLCC-20
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC-20 socket compatible)
Packaging Tape & Reel (-W suffix) —
Cascade Support Yes (with other EPC2 devices) —
Bilang ng Pin 20 —
Lead-Free / RoHS [DATA_NEEDED: RoHS status for -W variant] —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial/commercial temp range]
Fungsi — Configuration device for SRAM-based LUT FPGAs
Density — [DATA_NEEDED: bitstream density in bits]
Programming Interface — JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster
In-System Programmable — Yes
Error Detection — 16-bit CRC on configuration frames
Configuration Modes Supported — FPP and PS (depends on host FPGA)
Cascadable — Yes (multiple EPC2 devices for larger bitstreams)
Open-Drain Status Pin — Yes (CONF_DONE / nSTATUS compatible)
Level ng MSL — [DATA_NEEDED: MSL rating]
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status]

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