EPM3064ALC44-10 vs EPM3064ALC44-10N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3064ALC44-10 disebabkan oleh Altera dan EPM3064ALC44-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3064ALC44-10 EPM3064ALC44-10N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 3000A —
Logic Elements / Macrocells 64 macrocells —
Number of Logic Array Blocks (LABs) 4 —
Usable Gates 1,250 1,250
Maximum User I/O Pins 34 —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency (fCNT) 192.3 MHz —
Maximum Operating Frequency (fMAX) [DATA_NEEDED: fMAX internal] —
Kemasan 44-PLCC (J-Lead) 44-pin PLCC (LC44)
Process Technology 0.30 µm CMOS EEPROM —
Programmability In-system programmable (JTAG IEEE 1149.1) —
MultiVolt I/O 2.5V / 3.3V / 5.0V interface compatible —
Suhu Operasi 0°C to +70°C (commercial) [DATA_NEEDED: commercial / industrial grade]
Status RoHS Compliant (lead-free L suffix indicates Pb-free package) Compliant
Jenis Pemasangan Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
Product Family — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Array Blocks (LABs) — 4
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Maximum Counter Frequency — 227.3 MHz
I/O Bank Voltage (VCCIO) — 3.0 V to 3.6 V (MultiVolt)
Configuration Memory — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant)
Open-Drain Output Option — Yes (per I/O pin)
Output Slew-Rate Control — Programmable

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