EPM5032DC-15 vs EPM5032DI-20 Comparison
Detailed side-by-side comparison of EPM5032DC-15 by Altera and EPM5032DI-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete
Specification Comparison
| Parameter | EPM5032DC-15 | EPM5032DI-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 (Altera legacy EPLD) |
| Device Type | UV-erasable EPLD (PAL-type CMOS) | — |
| Usable Gates | 600 | — |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Logic Family | CMOS, TTL-compatible I/O | — |
| Programmable Pins | 16 bidirectional I/O + 4 dedicated input = 20 | — |
| Total Package Pins | 28 | — |
| Package | CERDIP-28 (windowed, through-hole) | Ceramic DIP-20 (windowed, UV-erasable) |
| Mounting Type | Through-Hole (DIP) | — |
| Operating Temperature | 0C to +70C (commercial) | Industrial (per 'I' suffix) |
| Erasure Method | UV light through ceramic quartz window | — |
| Process Technology | CMOS | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Architecture | — | CMOS PAL-type EPLD with PIA |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Product Terms | — | 320 (maximum) |
| Flip-Flops | — | 16 (one per macrocell) |
| Maximum Clock Frequency | — | 62.5 MHz |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Programming | — | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | — | Altera MAX+PLUS II (legacy) |