EPM5032DC20 vs EPM5032DI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC20 sa pamamagitan ng Altera at EPM5032DI-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DC20 | EPM5032DI-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable PLD (CPLD class) | — |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (Fmax) | 71.4 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 (bidirectional) | — |
| Total Inputs (max) | 24 | — |
| Output Macrocells | 16 | — |
| Clock Inputs | 1 (global) | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | CMOS PAL-type EPLD with PIA |
| Process Technology | CMOS | — |
| Packhaging | 20-pin Ceramic DIP (DC) with UV window | Ceramic DIP-20 (windowed, UV-erasable) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Family | — | MAX 5000 (Altera legacy EPLD) |
| Bidirectional I/O Pins | — | 16 |
| Product Terms | — | 320 (maximum) |
| Flip-Flops | — | 16 (one per macrocell) |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Programming | — | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |