EPM5032JC25 vs EPM5032DC-25 比較
詳細並排比較 EPM5032JC25 由 Altera 與 EPM5032DC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032JC25 | EPM5032DC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | — |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | — |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs to Array | 24 | — |
| 輸出數量 | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | PAL-Type, Single-LAB, 32-Macrocell |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| 供應電壓 | 5 V (TTL-level I/O) | — |
| 封裝 | 28-pin PLCC (JC) | CDIP-28 (Windowed Ceramic DIP-28) |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Lead Free / RoHS Compliant (per distributor listings) |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | — | 32 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Process Technology | — | CMOS, EPROM (UV-Erasable) |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |