EPM5032LC-20 vs EPM5032JC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-20 sa pamamagitan ng Altera at EPM5032JC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032LC-20 | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | UV-erasable Programmable Logic Device (PLD) |
| Usable Gates | 600 gates | — |
| Macrocells | 32 | 32 |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Supply Voltage (VCC) | 5 V ±5% | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | — |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs | 24 | 24 |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | 68-pin JLCC (windowed ceramic) |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Level ng MSL | [DATA_NEEDED: MSL] | — |
| Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Architecture | — | PAL-type AND-OR array with PIA interconnect |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera MAX 5000) |