EPM5192GC-2 vs EPM5192GM Comparison

Detailed side-by-side comparison of EPM5192GC-2 by Altera and EPM5192GM by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192GC-2 EPM5192GM
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 5000 —
Macrocells 192 —
Logic Array Blocks 16 (LABs of 16 macrocells each) —
Usable I/O Pins [DATA_NEEDED: exact user I/O count for PGA package] —
Propagation Delay (tPD) 12 ns typical (-2 grade) —
Counter Frequency 100 MHz minimum —
Supply Voltage (VCC) 5 V nominal —
Technology CMOS EPROM CMOS
Programmable Technology UV-erasable / one-time programmable —
Programming Toolchain Altera MAX+PLUS II —
Package Type Pin Grid Array (PGA), ceramic —
Operating Temperature Commercial (0C to +70C) [DATA_NEEDED: commercial/industrial/military grade]
Speed Grade -2 —
RoHS Status Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) Non-compliant (contains lead in ceramic PGA)
Mounting Type Through-hole (PGA socket) Through-Hole (PGA)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (PLD)
Number of Macrocells — 192
Usable Gates — 3,750
Pin-to-Pin Delay (tPD) — 15 ns (fastest speed grade); 55 ns (this part)
Counter Frequency (fCNT) — up to 76.9 MHz
Propagation Delay (tPD, this part) — 55 ns
Package — CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed)
Erasure Method — UV (windowed ceramic package)
Supply Voltage — [DATA_NEEDED: typical VCC range]
Maximum User I/O — [DATA_NEEDED: exact I/O count for CPGA-84]
Process Node — [DATA_NEEDED: CMOS process geometry]
Programming Interface — JTAG-compatible (per MAX 5000 family)

Datasheets & Resources

Browse All Products Create BOM Request Quote