EPM5192GC-2 vs EPM5192GM Comparison
Detailed side-by-side comparison of EPM5192GC-2 by Altera and EPM5192GM by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GC-2 | EPM5192GM |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $58.00 |
| Family | MAX 5000 | β |
| Macrocells | 192 | β |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | β |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | β |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | β |
| Counter Frequency | 100 MHz minimum | β |
| Supply Voltage (VCC) | 5 V nominal | β |
| Technology | CMOS EPROM | CMOS |
| Programmable Technology | UV-erasable / one-time programmable | β |
| Programming Toolchain | Altera MAX+PLUS II | β |
| Package Type | Pin Grid Array (PGA), ceramic | β |
| Operating Temperature | Commercial (0C to +70C) | [DATA_NEEDED: commercial/industrial/military grade] |
| Speed Grade | -2 | β |
| RoHS Status | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | Non-compliant (contains lead in ceramic PGA) |
| Mounting Type | Through-hole (PGA socket) | Through-Hole (PGA) |
| Product Family | β | MAX 5000 |
| Device Type | β | UV Erasable Programmable Logic Device (PLD) |
| Number of Macrocells | β | 192 |
| Usable Gates | β | 3,750 |
| Pin-to-Pin Delay (tPD) | β | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | β | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | β | 55 ns |
| Package | β | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Erasure Method | β | UV (windowed ceramic package) |
| Supply Voltage | β | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | β | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | β | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | β | JTAG-compatible (per MAX 5000 family) |