EPM5192GC-2 vs EPM5192GM 对比

详细并排对比 EPM5192GC-2 出自 Altera 和 EPM5192GM 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192GC-2 EPM5192GM
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $92.00 $58.00
Family MAX 5000 —
Macrocells 192 —
Logic Array Blocks 16 (LABs of 16 macrocells each) —
Usable I/O Pins [DATA_NEEDED: exact user I/O count for PGA package] —
Propagation Delay (tPD) 12 ns typical (-2 grade) —
Counter Frequency 100 MHz minimum —
Supply Voltage (VCC) 5 V nominal —
Technology CMOS EPROM CMOS
Programmable Technology UV-erasable / one-time programmable —
Programming Toolchain Altera MAX+PLUS II —
Package Type Pin Grid Array (PGA), ceramic —
工作温度 Commercial (0C to +70C) [DATA_NEEDED: commercial/industrial/military grade]
Speed Grade -2 —
RoHS 状态 Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) Non-compliant (contains lead in ceramic PGA)
安装类型 Through-hole (PGA socket) Through-Hole (PGA)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (PLD)
Number of Macrocells — 192
Usable Gates — 3,750
Pin-to-Pin Delay (tPD) — 15 ns (fastest speed grade); 55 ns (this part)
Counter Frequency (fCNT) — up to 76.9 MHz
Propagation Delay (tPD, this part) — 55 ns
封装 — CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed)
Erasure Method — UV (windowed ceramic package)
电源电压 — [DATA_NEEDED: typical VCC range]
Maximum User I/O — [DATA_NEEDED: exact I/O count for CPGA-84]
Process Node — [DATA_NEEDED: CMOS process geometry]
Programming Interface — JTAG-compatible (per MAX 5000 family)

数据手册与资源

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