EPM5192GC-2 vs EPM5192GM Vergleich
Detaillierter Direktvergleich von EPM5192GC-2 von Altera und EPM5192GM von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192GC-2 | EPM5192GM |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $92,00 | $58,00 |
| Family | MAX 5000 | — |
| Macrocells | 192 | — |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | — |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | — |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | — |
| Counter Frequency | 100 MHz minimum | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Technology | CMOS EPROM | CMOS |
| Programmable Technology | UV-erasable / one-time programmable | — |
| Programming Toolchain | Altera MAX+PLUS II | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Betriebstemperatur | Commercial (0C to +70C) | [DATA_NEEDED: commercial/industrial/military grade] |
| Speed Grade | -2 | — |
| RoHS-Status | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | Non-compliant (contains lead in ceramic PGA) |
| Montageart | Through-hole (PGA socket) | Through-Hole (PGA) |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (PLD) |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Gehäuse | — | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| Erasure Method | — | UV (windowed ceramic package) |
| Versorgungsspannung | — | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |
| Programming Interface | — | JTAG-compatible (per MAX 5000 family) |