EPM5192JC-ES vs EPM5192JC तुलना
विस्तृत दोनों ओर की तुलना EPM5192JC-ES द्वारा Intel और EPM5192JC द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5192JC-ES | EPM5192JC |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| पैकेज | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | 68-pin PLCC (JC) windowed ceramic |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| ऑपरेटिंग तापमान | [DATA_NEEDED: operating temperature range for ES grade] | [DATA_NEEDED: commercial / industrial / military grade] |
| सप्लाई वोल्टेज | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC nominal] |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera marking not RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL स्तर | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |