EPM5192JC-ES vs EPM5192JC68 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-ES sa pamamagitan ng Intel at EPM5192JC68 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC-ES EPM5192JC68
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family MAX 5000 MAX 5000
Device Type CPLD (EPLD) —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
Interconnect Programmable Interconnect Array (PIA) —
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) UV-Erasable EPROM
Packhaging 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) —
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC socket compatible)
Technology CMOS —
Programming Altera MAX+PLUS II or compatible programmer —
Temperature na Operasyon [DATA_NEEDED: operating temperature range for ES grade] 0C to 70C (commercial, JC suffix)
Volte ng Pagbibigay [DATA_NEEDED: VCC nominal] [DATA_NEEDED: VCC]
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] 76
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] —
Level ng MSL [DATA_NEEDED: MSL rating] —
Note Datasheet source: Altera MAX 5000 family document, 52 pages —
Product Type — EPLD (Erasable Programmable Logic Device)
Logic Elements / Macrocells — 192 macrocells
Bilang ng Pins — 68
Package Type — PLCC-68 (J-Lead)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD]
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX]
Programmable Interconnect — Programmable Logic Array + Macrocells
Dedicated Inputs — 12
Clock Pins — 4 dedicated
Programming Tool — MAX+PLUS II (legacy)

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