EPM5192JC68 vs EPM5192JC Comparison

Detailed side-by-side comparison of EPM5192JC68 by Altera and EPM5192JC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC68 EPM5192JC
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.85 $16.40
Device Family MAX 5000 β€”
Product Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Elements / Macrocells 192 macrocells β€”
User I/O Pins 76 β€”
Number of Pins 68 β€”
Package Type PLCC-68 (J-Lead) β€”
Operating Temperature 0C to 70C (commercial, JC suffix) [DATA_NEEDED: commercial / industrial / military grade]
Supply Voltage [DATA_NEEDED: VCC] [DATA_NEEDED: VCC nominal]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD] β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX] β€”
Configuration Memory UV-Erasable EPROM β€”
Programmable Interconnect Programmable Logic Array + Macrocells β€”
Dedicated Inputs 12 β€”
Clock Pins 4 dedicated β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: original Altera marking not RoHS]
Programming Tool MAX+PLUS II (legacy) β€”
Series β€” EPM5192 (Classic / MAX-class)
Macrocells β€” 192
Logic Array Blocks (LABs) β€” 12
Interconnect Architecture β€” Programmable Interconnect Array (PIA)
Process Technology β€” CMOS EPROM (UV-erasable)
Package β€” 68-pin PLCC (JC) windowed ceramic
Programming Method β€” UV-erase + EPROM programmer
Non-Volatile Configuration β€” Yes (EPROM cell array)
Logic Family β€” Classic CPLD (EPM5xxx series)
Propagation Delay β€” [DATA_NEEDED: tpd spec by speed grade]

Datasheets & Resources

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