EPM5192JC68 vs EPM5192JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC68 sa pamamagitan ng Altera at EPM5192JC sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC68 EPM5192JC
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family MAX 5000 —
Product Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Elements / Macrocells 192 macrocells —
User I/O Pins 76 —
Bilang ng Pins 68 —
Package Type PLCC-68 (J-Lead) —
Temperature na Operasyon 0C to 70C (commercial, JC suffix) [DATA_NEEDED: commercial / industrial / military grade]
Volte ng Pagbibigay [DATA_NEEDED: VCC] [DATA_NEEDED: VCC nominal]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD] —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX] —
Configuration Memory UV-Erasable EPROM —
Programmable Interconnect Programmable Logic Array + Macrocells —
Dedicated Inputs 12 —
Clock Pins 4 dedicated —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: original Altera marking not RoHS]
Programming Tool MAX+PLUS II (legacy) —
Series — EPM5192 (Classic / MAX-class)
Macrocells — 192
Logic Array Blocks (LABs) — 12
Interconnect Architecture — Programmable Interconnect Array (PIA)
Process Technology — CMOS EPROM (UV-erasable)
Packhaging — 68-pin PLCC (JC) windowed ceramic
Programming Method — UV-erase + EPROM programmer
Non-Volatile Configuration — Yes (EPROM cell array)
Logic Family — Classic CPLD (EPM5xxx series)
Propagation Delay — [DATA_NEEDED: tpd spec by speed grade]

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