EPM5192JC68 vs EPM5192JC Perbandingan
Perbandingan bersamaan detil EPM5192JC68 dari Altera dan EPM5192JC dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5192JC68 | EPM5192JC |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 192 macrocells | — |
| User I/O Pins | 76 | — |
| Jumlah Pin | 68 | — |
| Package Type | PLCC-68 (J-Lead) | — |
| Suhu Kerja | 0C to 70C (commercial, JC suffix) | [DATA_NEEDED: commercial / industrial / military grade] |
| Tegangan Pemuat | [DATA_NEEDED: VCC] | [DATA_NEEDED: VCC nominal] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Programmable Interconnect | Programmable Logic Array + Macrocells | — |
| Dedicated Inputs | 12 | — |
| Clock Pins | 4 dedicated | — |
| Tipe Mounting | Surface Mount (PLCC socket compatible) | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera marking not RoHS] |
| Programming Tool | MAX+PLUS II (legacy) | — |
| Series | — | EPM5192 (Classic / MAX-class) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Paket | — | 68-pin PLCC (JC) windowed ceramic |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |