EPM5192LC-2N vs EPM5192LC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-2N sa pamamagitan ng Altera at EPM5192LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-2N EPM5192LC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000 CPLD
Macrocells 192 —
Flip-Flops 192 —
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) —
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) JLCC (J-Lead Ceramic Chip Carrier)
Speed Grade -2 (tPD approximately 25 ns) -35
Propagation Delay (typical) 25 ns —
Volte ng Pagbibigay 5 V (typical) —
Programmability UV-erasable EPROM cell —
Uri ng Pagpapasok Surface Mount (LC package) Surface Mount
Temperature na Operasyon Commercial (0C to +70C) - inferred from speed-grade -2 designation Commercial (0C to +70C) per LC suffix
Tindminan RoHS Compliant (per -N lead-free suffix) Non-compliant (ceramic hermetic package)
Lead-Free Yes (per -N suffix) —
Architecture Programmable Logic Array (PLA) with global PIA LAB-based with Programmable Interconnect Array (PIA)
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) —
Series — MAX 5000
Logic Elements / Macrocells — 192 macrocells
Pin-to-Pin Delay (tPD) — 35 ns
Programmable Type — UV-Erasable / OTP (EPROM-based)
Logic Voltage — 5 V TTL-compatible I/O
Programming Method — Altera legacy programmer (EPROM-based)
I/O Standard — TTL
Katayuan ng Lifecycle — Obsolete - last-time-buy stock only
Datasheet Document — Altera MAX 5000 family datasheet (per alldatasheet.com)

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