EPM7128BTC100-10 vs EPM7128STI100-10N Comparison
Detailed side-by-side comparison of EPM7128BTC100-10 by Intel and EPM7128STI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128BTC100-10 - MAX 7000B CPLD, 128 Macrocells, 10ns | Intel
EPM7128BTC100-10 ⚠ Last Time BuyAltera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128BTC100-10 | EPM7128STI100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 7000B | MAX 7000S |
| Macrocells | 128 | 128 |
| Usable Gates | 2.5K | 2,500 (up to 5,000 family max) |
| User I/Os | 84 | — |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | 8 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | 125 MHz | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 3.3 V (5V tolerant inputs) | — |
| Package | TQFP-100 | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| RoHS Status | Compliant (lead-free) | [DATA_NEEDED: RoHS status] |
| Technology | CMOS EEPROM | — |
| Architecture | — | CMOS EEPROM-based CPLD |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 175.4 MHz |
| Supply Voltage (VCC) | — | 5 V |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| JTAG Boundary-Scan | — | Yes (BST) |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Open-Drain I/O Option | — | Available (per MAX 7000A feature set) |