EPM7128BTC100-10 - MAX 7000B CPLD, 128 Macrocells, 10ns | Intel
MPN: EPM7128BTC100-10 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.45 | $6,225.00 |
| 1,000 | $11.2 | $11,200.00 |
Drop-in alternatives for EPM7128BTC100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
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EPM7128AETC100-10N
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View Datasheet βEPM7128ATC100-10
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View Datasheet βEPM7128BTC100-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000B |
| Macrocells | 128 |
| Usable Gates | 2.5K |
| User I/Os | 84 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Frequency (fCNT) | 125 MHz |
| Core Voltage (VCCINT) | 2.5 V |
| I/O Voltage (VCCIO) | 3.3 V (5V tolerant inputs) |
| Package | TQFP-100 |
| Mounting Type | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature | 0C to +70C (commercial) |
| RoHS Status | Compliant (lead-free) |
| Technology | CMOS EEPROM |
EPM7128BTC100-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 2) |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | GND β Ground |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | GND β Ground |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | I/O β User I/O pin (bank 3) |
| Pin 55 | GND β Ground |
| Pin 56 | TDI β JTAG Test Data In (dedicated, 4-pin JTAG) |
| Pin 57 | TMS β JTAG Test Mode Select (dedicated) |
| Pin 58 | TCK β JTAG Test Clock (dedicated) |
| Pin 59 | TDO β JTAG Test Data Out (dedicated) |
| Pin 60 | GND β Ground |
| Pin 61 | VCCINT β Core supply 2.5V |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | GND β Ground |
| Pin 73 | VCCIO β I/O supply 3.3V |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | I/O β User I/O pin (bank 4) |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | I/O β User I/O pin (bank 4) |
| Pin 79 | I/O β User I/O pin (bank 4) |
| Pin 80 | I/O β User I/O pin (bank 4) |
| Pin 81 | I/O β User I/O pin (bank 4) |
| Pin 82 | I/O β User I/O pin (bank 4) |
| Pin 83 | I/O β User I/O pin (bank 4) |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β User I/O pin (bank 1) |
| Pin 86 | I/O β User I/O pin (bank 1) |
| Pin 87 | I/O β User I/O pin (bank 1) |
| Pin 88 | I/O β User I/O pin (bank 1) |
| Pin 89 | I/O β User I/O pin (bank 1) |
| Pin 90 | I/O β User I/O pin (bank 1) |
| Pin 91 | I/O β User I/O pin (bank 1) |
| Pin 92 | I/O β User I/O pin (bank 1) |
| Pin 93 | I/O β User I/O pin (bank 1) |
| Pin 94 | GND β Ground |
| Pin 95 | I/O β User I/O pin (bank 1) |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | I/O β User I/O pin (bank 1) |
| Pin 100 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128BTC100-10 is suitable for 6 applications: Microprocessor Address Decoding and Glue Logic, PCI / ISA Bus Bridge and Peripheral Expansion, Power Supply Sequencing and Supervisor Logic, Industrial Control and Factory Automation, Legacy Telecom and Networking Backplane Glue Logic, State-Machine Control for Test & Measurement.
Microprocessor Address Decoding and Glue Logic
The EPM7128BTC100-10 is a classic choice for 8/16/32-bit microprocessor address decoding, chip-select generation, and bus-interface glue logic. With 128 macrocells and 84 user I/Os, it has ample capacity to replace 5 to 10 discrete 74LS/74HC decoder and latch ICs on a legacy 386/486/Pentium board while saving roughly 60 percent of the PCB area. The 10 ns tPD delivers deterministic propagation delay regardless of which macrocell is used, so address-to-chip-select timing stays within the CPU's tACC budget across all operating conditions. JTAG/ISP lets engineers iterate on the decoding map in-circuit, eliminating the PROM burn-and-swap cycle that discrete PALs required. In production designs the device is typically powered from a 3.3V rail with the VCCINT 2.5V generated by an LDO, and decoupling is 0.1 uF plus 10 uF bulk per the MAX 7000B reference schematic.
Recommended
PCI / ISA Bus Bridge and Peripheral Expansion
The EPM7128BTC100-10 is widely deployed as a PCI or ISA peripheral bridge, mapping memory and I/O windows between a CPU bus and an FPGA, ASIC, or legacy peripheral. The 84 user I/Os in TQFP-100 give engineers enough pins to break out an entire 32-bit data bus plus 24-bit address plus 8 chip selects without external muxes. The 5V-tolerant inputs (with VCCIO at 3.3V) interface directly to PCI 5V signaling, eliminating the level shifters that a 3.3V-only CPLD would require. The deterministic 10 ns tPD is critical for meeting PCI's 7 ns setup-time budget at 33 MHz when one nano second of tCO from the CPLD is added. Designers also use the JTAG port to field-update the bridge map when adding new peripherals, an upgrade path not available with discrete 74-series logic.
Recommended
Power Supply Sequencing and Supervisor Logic
The EPM7128BTC100-10 fits naturally into multi-rail ATX or telecom power-supply sequencers, where 5 to 10 power rails must power up in a specific order with programmable delays and PG (power-good) interlocking. Each macrocell can implement a state machine or delay timer, and the 84 I/Os comfortably handle the rail count plus PG feedback plus fault-flag outputs. Because the device is non-volatile EEPROM-based, sequencing state survives brown-outs and power-cycles, a feature FPGAs lack without an external configuration PROM. The 2.5V core and 3.3V I/O are compatible with modern POL (point-of-load) converters, while the 5V-tolerant inputs accept TTL-level PG signals from legacy supervisors. Estimated: typical quiescent power at room temperature is 250 mW with all macrocells toggling at 10 MHz.
Recommended
Industrial Control and Factory Automation
The EPM7128BTC100-10 (commercial 0 to 70C) and its automotive-grade sibling EPM7128AETC100-10N (-40 to +125C) are commonly deployed in PLCs, motor controllers, and factory-automation backplanes where deterministic timing and high I/O count matter. The 84 I/Os accept 24V industrial signals through external optocouplers, while outputs drive 5V relay coils or 24V drivers via external transistors. The device's deterministic 10 ns tPD is critical for closed-loop control where the controller-to-actuator latency budget is 100 micro seconds end-to-end. Non-volatile configuration means PLC firmware revisions persist across factory power cycles without an external boot PROM. Estimated: at 70C ambient with 84 I/Os switching at 1 MHz, the device dissipates roughly 400 mW and requires 200 mm squared of copper pour on the top layer.
Recommended
Legacy Telecom and Networking Backplane Glue Logic
The EPM7128BTC100-10 has been a workhorse in legacy telecom and networking equipment such as T1/E1 line cards, central-office switches, and backplane controllers. The TQFP-100 footprint exposes enough I/Os to drive an entire 8-bit datacom backplane plus HDLC framing logic plus LEDs and alarm outputs. The non-volatile EEPROM core ensures that the backplane configuration survives the brown-outs that occur during central-office battery plant transitions, eliminating the FPGA-style in-rush storm that can collapse the 48V battery bus. JTAG/ISP enables field re-provisioning when a new line-card type is added to the chassis. Estimated: in a 48-port line-card design the CPLD typically replaces 12 to 18 discrete 74FCT and 74ABT devices, cutting board area by roughly 50 percent.
Recommended
State-Machine Control for Test & Measurement
The EPM7128BTC100-10 is well suited for instrument front-panel state machines in oscilloscopes, logic analyzers, and bench multimeters, where 32 to 128 logic equations drive rotary-encoder decoding, button debouncing, LCD muxing, and menu navigation. The deterministic tPD of 10 ns is more than adequate for human-perceptible UI timing (10 ms to 100 ms), and the EEPROM core retains the menu state through power cycles. The 84 I/Os comfortably break out a 4-line rotary encoder plus 16-key keypad plus 4x40 LCD plus 8 status LEDs plus UART debug port. JTAG lets the firmware team iterate on the menu flow without re-spinning the front-panel PCB. Designers typically pair the CPLD with a small microcontroller for the LCD bitmap rendering, splitting deterministic control-plane work from the processor's variable-latency update path.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128BTC100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128BTC100-7 | EPM7128BTC100-4N | EPM7128AETC100-10N | EPM7128ATC100-10 | EPM7128AEFC100-5 |
|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel | Intel | Intel | Intel | Intel (originally Altera) | Intel (originally Altera) |
| Family | MAX 7000B | MAX 7000B | MAX 7000B | MAX 7000B (automotive) | MAX 7000A | MAX 7000B (automotive) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns | 4.5 ns | 10 ns | 10 ns | 5 ns |
| Maximum Frequency (fCNT) | 125 MHz | 150 MHz | 192 MHz | 125 MHz | 125 MHz | [DATA_NEEDED] |
| VCCINT (Core Voltage) | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 5.0 V (MAX 7000A) | 2.5 V |
| Temperature Grade | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | -40C to +125C (automotive) | 0C to +70C | -40C to +125C (automotive) |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Obsolete | Obsolete |
Key Differentiators
- Industry-standard 100-pin TQFP footprint shared across the entire MAX 7000B 128-macrocell family (vs Xilinx XC9572XL (100-pin TQFP/VQFP))
- MultiVolt interface for direct 5V/3.3V/2.5V mixed-voltage system integration (vs Lattice ispMACH 4000V (LC4128V))
- Deterministic 10 ns tPD independent of logic placement and routing density (vs SRAM-based low-density FPGA (e.g. Lattice iCE40))
Design Notes
The MAX 7000B family uses a split-rail supply: VCCINT must be 2.5V and VCCIO must be 3.3V, with both rails ramped monotonically within the datasheet's tRAMP specification. Power sequencing is not strictly required, but if VCCIO ramps before VCCINT the I/O drivers will draw elevated current through the ESD cells. Decoupling per the datasheet is one 0.1 uF X7R ceramic per VCCINT pin and per VCCIO pin, plus one 10 uF tantalum or ceramic bulk capacitor near each supply pin. Estimated: total supply current at 125 MHz toggle with all 84 I/Os active is approximately 100 mA on VCCINT and 25 mA on VCCIO.
TQFP-100 with 0.5 mm lead pitch requires a 4-layer PCB with a continuous ground plane under the device to provide both thermal spreading and a low-impedance return path for the high-speed I/O. Route the four JTAG pins (TCK, TMS, TDI, TDO) on the top layer away from clock edges, and place a 10 kohm pull-down on TCK and 10 kohm pull-up on TMS as recommended by IEEE 1149.1. The TDO output should be series-terminated with 33 ohm if the trace length to the next JTAG device exceeds 50 mm. Ground vias should be placed at each GND pin with thermal relief to the inner ground plane.
Three common pitfalls in MAX 7000B designs: (1) driving 5V TTL inputs into the device without verifying that the input pin is configured as 5V-tolerant in the Quartus pin planner; (2) exceeding the 25 mA per-pin DC output current limit when driving LED or relay loads directly, which causes long-term electromigration failure; (3) failing to enable the JTAG USERCODE instruction in the programming file, which prevents in-field identification of the programmed image. Designers should also avoid connecting unused I/O pins to long traces or antennas - configure them as output driving ground to reduce EMI susceptibility.
Compliance Information
RoHS compliant per Intel/Altera MAX 7000B product page. Lead-free TQFP-100 package. Not AEC-Q100 qualified in the standard EPM7128BTC100-10 variant; the EPM7128AETC100-10N is the automotive-grade equivalent. Halogen-free status not explicitly stated in the verified distributor data.
