EPM7128BTC100-10 vs EPM7128STI100-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128BTC100-10 sa pamamagitan ng Intel at EPM7128STI100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128BTC100-10 - MAX 7000B CPLD, 128 Macrocells, 10ns | Intel
EPM7128BTC100-10 ⚠ Huling PagbiliAltera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128BTC100-10 | EPM7128STI100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | MAX 7000B | MAX 7000S |
| Macrocells | 128 | 128 |
| Usable Gates | 2.5K | 2,500 (up to 5,000 family max) |
| User I/Os | 84 | — |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | 8 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | 125 MHz | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 3.3 V (5V tolerant inputs) | — |
| Packhaging | TQFP-100 | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| Tindminan RoHS | Compliant (lead-free) | [DATA_NEEDED: RoHS status] |
| Technology | CMOS EEPROM | — |
| Architecture | — | CMOS EEPROM-based CPLD |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 175.4 MHz |
| Supply Voltage (VCC) | — | 5 V |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| JTAG Boundary-Scan | — | Yes (BST) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Open-Drain I/O Option | — | Available (per MAX 7000A feature set) |