EPM9560ARC208-10 vs EPM9320RC208-20 Comparison

Detailed side-by-side comparison of EPM9560ARC208-10 by Intel and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARC208-10 EPM9320RC208-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $21.90
Device Family MAX 9000A (Multiple Array MatriX) β€”
Programmable Logic Type CPLD (Complex Programmable Logic Device) β€”
Usable Gates 12,000 gates 6,000
Macrocells 560 macrocells 320
Logic Array Blocks 35 LABs β€”
User I/O Pins 153 I/O β€”
Propagation Delay (tPD) 10 ns (speed grade -10) β€”
Internal Frequency 144.9 MHz β€”
Supply Voltage 5.0 V β€”
Logic Family CMOS β€”
Configuration Technology EEPROM (non-volatile, in-system programmable) β€”
JTAG Interface IEEE 1149.1 boundary-scan (ISP) β€”
Operating Temperature 0 C to +70 C (commercial) 0 Β°C to 70 Β°C (commercial)
Package 208-pin RQFP (PowerQuad Flat Pack) with exposed pad 208-RQFP, exposed pad (208-BFQFP)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] β€”
Pin Count 208 pins β€”
Family β€” MAX 9000
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 20
Maximum I/O Pins β€” 132
Propagation Delay (tPD max) β€” 20 ns
Supply Voltage (VCCINT) β€” 4.75 V to 5.25 V
Programming Technology β€” EEPROM, in-system programmable (ISP)
Boundary-Scan Interface β€” IEEE Std. 1149.1 (JTAG)
Architecture β€” Multiple Array Matrix (MAX), 3rd generation
Process Technology β€” CMOS, 5.0 V EEPROM
Reprogrammability β€” Yes, unlimited ISP cycles

Datasheets & Resources

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