EPM9560RC210-20 vs EPM9560RC208-20N Comparison
Detailed side-by-side comparison of EPM9560RC210-20 by Altera and EPM9560RC208-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC210-20 | EPM9560RC208-20N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Package | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) | 208-pin RQFP (PowerQuad Flat Pack) |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Clock-to-Output (tCO) | 12 ns | — |
| Maximum User I/O | [DATA_NEEDED: 212 I/O per datasheet, package-dependent] | — |
| Supply Voltage | 5 V | 5.0 V |
| Process Technology | 0.65 um EEPROM | — |
| In-System Programmability | Yes (MAX+PLUS II flow) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Operating Temperature | [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | RoHS3 Compliant (per supplier listing) | Lead-free (N suffix) |
| Device Family | — | MAX 9000 (EPM9560) |
| Propagation Delay (tPD) | — | 20 ns |
| User I/O Pins | — | 149 |
| Configuration Technology | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Logic Architecture | — | Multiple Array MatriX (MAX), third-generation CMOS EEPROM |
| Flip-Flops | — | 772 (per EPM9560 series data) |
| Speed Grade | — | -20 (20 ns) |
| MSL Level | — | [DATA_NEEDED: MSL level] |