EPM9560RC210-20 vs EPM9560RC208-20N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC210-20 disebabkan oleh Altera dan EPM9560RC208-20N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM9560RC210-20 EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM9560RC210-20 EPM9560RC208-20N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Family MAX 9000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 —
Kemasan RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) 208-pin RQFP (PowerQuad Flat Pack)
Pin-to-Pin Delay (tPD) 20 ns —
Clock-to-Output (tCO) 12 ns —
Maximum User I/O [DATA_NEEDED: 212 I/O per datasheet, package-dependent] —
Tegangan Pemberi Arus 5 V 5.0 V
Process Technology 0.65 um EEPROM —
In-System Programmability Yes (MAX+PLUS II flow) Yes, via IEEE Std. 1149.1 JTAG
Boundary-Scan (JTAG) IEEE Std 1149.1 compliant —
Suhu Operasi [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] [DATA_NEEDED: operating temperature range]
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS RoHS3 Compliant (per supplier listing) Lead-free (N suffix)
Device Family — MAX 9000 (EPM9560)
Propagation Delay (tPD) — 20 ns
User I/O Pins — 149
Configuration Technology — EEPROM (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Logic Architecture — Multiple Array MatriX (MAX), third-generation CMOS EEPROM
Flip-Flops — 772 (per EPM9560 series data)
Speed Grade — -20 (20 ns)
Aras MSL — [DATA_NEEDED: MSL level]

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