EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera
MPN: EPM9560RC210-20 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $75 | $75.00 |
| 10 | $70 | $700.00 |
| 100 | $65 | $6,500.00 |
| 500 | $62.5 | $31,250.00 |
| 1,000 | $60 | $60,000.00 |
Drop-in alternatives for EPM9560RC210-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM9560RC210-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Package | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Clock-to-Output (tCO) | 12 ns |
| Supply Voltage | 5 V |
| Process Technology | 0.65 um EEPROM |
| In-System Programmability | Yes (MAX+PLUS II flow) |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant |
| Mounting Type | Surface Mount |
| RoHS Status | RoHS3 Compliant (per supplier listing) |
EPM9560RC210-20 Pin Configuration
| Pin 1 | I/O β User I/O pin (per datasheet pin table) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | GLOBAL_CLK β Global clock input |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | TDI β JTAG Test Data In |
| Pin 12 | TMS β JTAG Test Mode Select |
| Pin 13 | TCK β JTAG Test Clock |
| Pin 14 | TDO β JTAG Test Data Out |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | GLOBAL_CLK β Global clock input |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | VCC β 5V supply |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | GLOBAL_OE β Global output enable |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | VCC β 5V supply |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | GLOBAL_CLK β Global clock input |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | VCC β 5V supply |
| Pin 54 | GND β Ground |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | GLOBAL_OE β Global output enable |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | VCC β 5V supply |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | GLOBAL_CLK β Global clock input |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | VCC β 5V supply |
| Pin 88 | GND β Ground |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | GLOBAL_OE β Global output enable |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | VCC β 5V supply |
| Pin 102 | GND β Ground |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | I/O β User I/O pin |
| Pin 108 | GLOBAL_CLK β Global clock input |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | VCC β 5V supply |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | GLOBAL_OE β Global output enable |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | I/O β User I/O pin |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | VCC β 5V supply |
| Pin 134 | GND β Ground |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | GLOBAL_CLK β Global clock input |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | VCC β 5V supply |
| Pin 152 | GND β Ground |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | GLOBAL_OE β Global output enable |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | I/O β User I/O pin |
| Pin 162 | I/O β User I/O pin |
| Pin 163 | I/O β User I/O pin |
| Pin 164 | VCC β 5V supply |
| Pin 165 | GND β Ground |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | I/O β User I/O pin |
| Pin 168 | I/O β User I/O pin |
| Pin 169 | I/O β User I/O pin |
| Pin 170 | I/O β User I/O pin |
| Pin 171 | GLOBAL_CLK β Global clock input |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | I/O β User I/O pin |
| Pin 174 | I/O β User I/O pin |
| Pin 175 | I/O β User I/O pin |
| Pin 176 | I/O β User I/O pin |
| Pin 177 | I/O β User I/O pin |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | I/O β User I/O pin |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | I/O β User I/O pin |
| Pin 182 | I/O β User I/O pin |
| Pin 183 | VCC β 5V supply |
| Pin 184 | GND β Ground |
| Pin 185 | I/O β User I/O pin |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | I/O β User I/O pin |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | I/O β User I/O pin |
| Pin 190 | GLOBAL_OE β Global output enable |
| Pin 191 | I/O β User I/O pin |
| Pin 192 | I/O β User I/O pin |
| Pin 193 | I/O β User I/O pin |
| Pin 194 | I/O β User I/O pin |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | VCC β 5V supply |
| Pin 197 | GND β Ground |
| Pin 198 | I/O β User I/O pin |
| Pin 199 | I/O β User I/O pin |
| Pin 200 | I/O β User I/O pin |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | GLOBAL_CLK β Global clock input |
| Pin 204 | I/O β User I/O pin |
| Pin 205 | I/O β User I/O pin |
| Pin 206 | I/O β User I/O pin |
| Pin 207 | I/O β User I/O pin |
| Pin 208 | I/O β User I/O pin |
| Pin 209 | I/O β User I/O pin |
| Pin 210 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC210-20 is suitable for 6 applications: Industrial Control Glue Logic, Microprocessor Peripheral Bus Bridge, Telecom Backplane Address Decoder, State-Machine Replacement for 74LS/74F Logic, Legacy Avionics and Military Systems, Instrumentation Test Equipment.
Industrial Control Glue Logic
The EPM9560RC210-20 fits industrial control glue-logic designs because its 560 macrocells and 5V I/O integrate directly with 5V TTL/CMOS peripherals such as 8255 PPI, 8259 PIC, and discrete 74LS logic. The deterministic 20ns pin-to-pin delay guarantees timing closure for address decoding, interrupt steering, and handshake generation without static timing analysis - a critical advantage for legacy PLC and CNC retrofits. The JTAG boundary-scan support per IEEE 1149.1 enables in-circuit board test of solder joints, simplifying manufacturing test. Per Altera's MAX 9000 datasheet, the EEPROM process means instant-on configuration with no boot PROM, reducing BOM cost and improving reliability in factory environments with frequent power cycling.
Recommended
Microprocessor Peripheral Bus Bridge
The EPM9560RC210-20 is well suited to bridge between microprocessors and peripheral buses thanks to its 164-212 user I/O and 20ns tPD, which comfortably decodes ISA or extended 8/16-bit bus address spaces without external latches. Per the MAX 9000 datasheet, the 560 macrocells handle full 24-bit address decode plus chip-select generation for memory banks, peripherals, and dual-port RAM. The 5V supply eliminates level shifters when interfacing to legacy MCUs such as 8051, 80188, or 68302 families. The on-chip EEPROM guarantees deterministic behavior at power-up, which is essential for boot ROM emulation and memory-mapped register decoding in industrial controllers.
Recommended
Telecom Backplane Address Decoder
Telecom backplane address decoder applications benefit from the EPM9560RC210-20's 560 macrocells and high I/O count, which can decode multi-drop backplane addresses for H.110/CT Bus or MVIP architectures. The -20ns tPD matches typical 33 MHz bus timing budgets with margin. According to the Altera MAX 9000 datasheet, the JTAG support simplifies ATEX and NEBS compliance testing on telecom boards. The 5V I/O is compatible with legacy TTL bus drivers, and the EEPROM configuration ensures no bus contention during hot-insertion events - critical for carrier-grade equipment requiring NEBS-3 compliance.
Recommended
State-Machine Replacement for 74LS/74F Logic
The EPM9560RC210-20 directly replaces multiple 74LS/74F discrete PLD chips with a single device, reducing PCB area and BOM count in legacy industrial and instrumentation designs. Per Altera's MAX 9000 datasheet, the 560 macrocells can implement approximately 50 to 80 PAL-equivalent state machines in one package. The deterministic timing preserves compatibility with existing schematics while the in-system programmability allows last-minute firmware changes without board re-spin. The 5V tolerance makes it a true drop-in for boards originally designed around 74LS logic families.
Recommended
Legacy Avionics and Military Systems
The EPM9560RC210-20 is commonly deployed in long-life-cycle avionics, military, and aerospace systems where the design is frozen but production continues for 15-25 years. The mature MAX 9000 family has extensive DO-254 and military pedigree with multiple temperature-grade variants available. Per Altera's product lifecycle documentation, the EEPROM process and 5V supply provide the radiation tolerance margin needed for avionics environments. The 210-pin RQFP package offers the highest I/O density in the family for ARINC 429, MIL-STD-1553, and discrete interface logic consolidation.
Recommended
Instrumentation Test Equipment
The EPM9560RC210-20 is used in bench-top and ATE instrumentation because its 560 macrocells can implement waveform sequencers, counter/timer trees, and front-panel multiplexers in one device. The 20ns tPD allows triggering and gating logic at speeds up to 50 MHz without metastability issues common in discrete logic. According to the Altera MAX 9000 datasheet, the JTAG interface enables straightforward integration with boundary-scan test infrastructure in manufacturing test. The 5V tolerance interfaces directly with TTL-compatible DACs, ADCs, and analog switches used in legacy instrumentation front-ends.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC210-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-20 | EPM9560RC208-20N | EPM9560RC208-20C | EPM9560RC208-21 | EPM9560RC208-15 |
|---|---|---|---|---|---|---|
| Package | RQFP-210 | RQFP-208 (2 pins less) | RQFP-208 | RQFP-208 | RQFP-208 | RQFP-208 |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Speed Grade (tPD) | 20 ns | 20 ns | 20 ns | 20 ns | 21 ns (+5% slower) | 15 ns (-25% faster) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Process Technology | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM | 0.65um EEPROM |
| JTAG Boundary-Scan | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 | IEEE 1149.1 |
| Lifecycle Status | Last-time-buy (mature) | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
| Approximate Unit Price (qty 100) | $65 | $55 (est.) | $60 (est.) | $55 (est.) | $50 (est.) | $80 (est.) |
Key Differentiators
- Highest-density MAX 9000 device with 560 macrocells (vs EPM9480RC208-15)
- 210-pin RQFP package for maximum I/O count (vs EPM9560RC208-20)
- -20 speed grade offers balanced performance/cost (vs EPM9560RC208-15)
- Mature production status with proven long-term supply (vs EPM9560ARC208-10)
Design Notes
The 210-pin RQFP package uses 0.5mm lead pitch with a body size of approximately 32mm x 32mm. Per Altera MAX 9000 PCB layout guidelines, allocate at least 4-layer PCB with continuous ground plane under the device to control switching noise. Use micro-via or via-in-pad if design rules allow, otherwise place ground vias in the land pattern area. Decoupling: at least four 0.1uF ceramic + one 10uF tantalum per VCC pin group, placed within 5mm of each VCC pin.
The EPM9560RC210-20 draws ICC of approximately 200-400 mA depending on logic utilization and toggle rate. Per Altera datasheet, unused I/O pins should be configured as outputs driving ground or defined inputs with pull-ups to minimize supply current. The 5V supply ramp must be monotonic; if not, hold OE low until VCC reaches 4.75V to prevent output buffer latch-up. Add a supervisory reset circuit to ensure clean power-up.
Global clock pins (GLOBAL_CLK) and global output-enable pins (GLOBAL_OE) must be assigned to dedicated package pins per the Altera MAX+PLUS II fitting report. These pins route directly to the LAB clock and OE trees - using them as user I/O loses the deterministic global-signal advantage. Keep high-speed clock traces short (<25mm) and impedance-matched (50 ohms) to avoid ringing. JTAG chain pins (TCK, TMS, TDI, TDO) require 10k pull-ups on TMS and TDI per IEEE 1149.1.
Compliance Information
RoHS3 compliant per Alibaba supplier listing. Lead-free confirmed. REACH and conflict-mineral declarations not stated in available data.
