EPM9560RC240-2 vs EPM9560RC240-15N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC240-2 disebabkan oleh Altera dan EPM9560RC240-15N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM9560RC240-2 EPM9560RC240-15N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Logic Elements 560 macrocells —
Usable Gates 12,000 12,000
Pin-to-Pin Delay 2 ns (speed grade -2) —
Maximum Frequency 100 MHz —
Tegangan Pemberi Arus 5 V 5.0 V
User I/O Count 212 —
Kemasan 240-pin RQFP (Metric QFP) RQFP-240 (240-pin Plastic Quad Flat Pack)
Jenis Pemasangan Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1), in-system programmable —
Non-Volatile Configuration Yes (EEPROM-based) —
Suhu Operasi [DATA_NEEDED: commercial/industrial grade] 0C to +70C (Commercial)
Status RoHS Non-compliant (5V RQFP, pre-RoHS era) [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Lead-Free No (legacy Sn/Pb process) —
Logic Block Count [DATA_NEEDED: LAB count] —
Series — MAX 9000
Macrocells — 560
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

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