EPM9560RCRC304-15 - MAX 9000 CPLD 560 Macro Cells | Altera
MPN: EPM9560RCRC304-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM9560RCRC304-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RC304-15
✅ Drop-In✓ In Stock
$9.4 / Unit
View Datasheet →EPM9560RC304-10
✅ Drop-In✓ In Stock
$17.6 / Unit
View Datasheet →EPM9560RC304-20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPM9560RC304-5
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPM9560RC304-3
✅ Drop-In✓ In Stock
$18.9 / Unit
View Datasheet →EPM9560RC304-2
✅ Drop-In✓ In Stock
$55 / Unit
View Datasheet →EPM9560RCRC304-15 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 (EPM9560) |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | 560 |
| Usable Gates | 12,000 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns |
| Maximum Frequency | 117.6 MHz |
| Supply Voltage | 5.0 V |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability (ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 (built-in) |
| Package | 304-pin RQFP (PowerQuad Flat Pack) |
| Mounting Type | Surface Mount |
| Architecture | Third-generation Multiple Array MatriX (MAX) |
EPM9560RCRC304-15 304-pin rqfp (powerquad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RCRC304-15 (304-pin rqfp (powerquad flat pack) package) with [DATA_NEEDED: user I/O pin count] pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RCRC304-15.
Refer to the datasheet for full pin configuration.
Estimated pin count: [DATA_NEEDED: user I/O pin count] pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RCRC304-15 is suitable for 6 applications: Legacy Industrial Control Backplane, 5 V Bus Bridging and Address Decoding, Telecommunications Line-Card Glue Logic, Test and Measurement Instrumentation, Legacy 74-Series Logic Replacement, Obsolete System Maintenance and Repair.
Legacy Industrial Control Backplane
The EPM9560RCRC304-15 fits legacy 5 V industrial control backplanes because it operates from a single 5.0 V supply and is directly compatible with 5 V TTL and CMOS logic levels, eliminating level shifters on existing boards. Its 560 macro cells and 12,000 usable gates absorb address decoding, chip-select generation, and bus arbitration that would otherwise require dozens of 74-series packages. The non-volatile EEPROM configuration makes the device live at power-up with no external configuration memory, which is critical for deterministic industrial startup. With a 15 ns pin-to-pin delay and 117.6 MHz maximum frequency, it meets the timing of classic backplane buses. The 304-pin RQFP package provides the I/O count needed for wide address and data buses, and the deterministic MAX 9000 interconnect guarantees fixed timing independent of placement and routing.
Recommended
5 V Bus Bridging and Address Decoding
The EPM9560RCRC304-15 is used as a 5 V bus bridge and address decoder where legacy processors and peripherals must be interconnected without redesigning the voltage domain. Its 5.0 V operation and 5 V-compatible I/O allow direct connection to classic microprocessors and memory buses, while 560 macro cells implement address decode, wait-state generation, and bus multiplexing in a single device. The 15 ns pin-to-pin propagation delay keeps decode paths fast enough for 5 V bus cycles, and the 117.6 MHz maximum frequency supports high-throughput glue logic. Because MAX 9000 routing is deterministic, worst-case decode timing is fixed and repeatable, unlike SRAM FPGA designs. The 304-pin RQFP package supplies enough pins for wide address, data, and control buses in a single footprint.
Recommended
Telecommunications Line-Card Glue Logic
The EPM9560RCRC304-15 serves telecommunications line-card glue logic where 5 V legacy cards require programmable interconnect between framers, controllers, and backplane interfaces. Its 560 macro cells and 12,000 usable gates implement state machines, FIFO control, and interrupt logic that would otherwise need many discrete logic ICs. The 15 ns pin-to-pin delay and 117.6 MHz maximum frequency support the timing of classic TDM and control buses, while non-volatile EEPROM configuration ensures the card is operational immediately at power-up without a configuration PROM. The 304-pin RQFP package provides the I/O density for wide line-card buses. Deterministic MAX 9000 interconnect gives repeatable timing across cards, simplifying qualification and sparing replacement in deployed telecom equipment.
Recommended
Test and Measurement Instrumentation
The EPM9560RCRC304-15 is used in test and measurement instrumentation for control-path logic, trigger sequencing, and interface glue in 5 V legacy instruments. Its 560 macro cells implement counters, comparators, and state machines, while the 15 ns pin-to-pin delay and 117.6 MHz maximum frequency provide the deterministic response needed for trigger and timing circuits. Non-volatile EEPROM configuration means the instrument boots instantly with no configuration load, which is important for standalone bench equipment. The 5.0 V supply and 5 V-compatible I/O match the logic levels of legacy instrument front ends and backplanes. The 304-pin RQFP package supports the wide control and data buses found in multi-channel instruments, and deterministic routing keeps timing repeatable across units.
Recommended
Legacy 74-Series Logic Replacement
The EPM9560RCRC304-15 replaces banks of discrete 74-series logic in existing 5 V designs, consolidating glue logic into one non-volatile programmable device. Its 560 macro cells and 12,000 usable gates absorb decoders, multiplexers, counters, and flip-flops that previously occupied many packages, reducing board area and part count. Because it operates at 5.0 V with 5 V-compatible I/O, it drops into legacy logic domains without level shifting, and its 15 ns pin-to-pin delay matches or beats discrete 74-series propagation delays. EEPROM configuration makes it live at power-up, preserving the instant-on behavior of discrete logic. The 304-pin RQFP package provides ample I/O for wide replacement logic, and deterministic MAX 9000 timing keeps behavior predictable.
Recommended
Obsolete System Maintenance and Repair
The EPM9560RCRC304-15 is a maintenance and repair part for deployed systems built around the MAX 9000 family, where the original 304-pin RQFP footprint and 5 V logic domain must be preserved. Because the device is obsolete, repair organizations source it through independent channels and rely on pin-compatible EPM9560 variants such as EPM9560RC304-15 to keep equipment running. Its 560 macro cells, 12,000 usable gates, and 15 ns pin-to-pin delay match the original design, so no firmware or board change is required. Non-volatile EEPROM configuration means a replacement device retains the programmed design without external memory. The 304-pin RQFP package ensures mechanical compatibility with existing sockets and reflow profiles.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RCRC304-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-15 | EPM9560RC304-10 | EPM9560RC304-20 | EPM9560RC304-5 |
|---|---|---|---|---|---|
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Macro Cells | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns | 10 ns | 20 ns | 5 ns |
| Maximum Frequency | 117.6 MHz | 117.6 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| JTAG ISP | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Non-volatile EEPROM configuration, live at power-up (vs EPM9560RC304-15)
- Deterministic 15 ns pin-to-pin timing (vs EPM9560RC304-10)
- 5 V native operation with 5 V-compatible I/O (vs EPM9560RC304-20)
Design Notes
The EPM9560RCRC304-15 requires a clean, well-regulated 5.0 V supply. Place a 0.1 uF ceramic decoupling capacitor on every VCC pin and a bulk 10 uF to 47 uF capacitor near the device to absorb switching transients from the high macro-cell count. Because the part is a 5 V EEPROM-based CPLD, inrush during power-up is modest, but the supply must reach the minimum 5 V threshold monotonically to guarantee correct EEPROM load and device initialization. Estimated: with 560 macro cells switching, dynamic current scales with clock frequency; verify the actual ICC against the MAX 9000 datasheet for your design's toggle rate.
Route the IEEE Std. 1149.1 JTAG signals (TDI, TDO, TMS, TCK) as short, controlled-impedance traces and keep TCK free of noise, since a glitch on TCK during in-system programming can corrupt the EEPROM configuration. Terminate TDI and TMS with pull-up resistors per the MAX 9000 datasheet recommendation, and provide a dedicated ground return for the JTAG chain. For the 304-pin RQFP package, use a solid ground plane under the device and keep high-speed I/O traces away from the JTAG pins to avoid coupling during programming.
The EPM9560RCRC304-15 is obsolete, so the biggest design pitfall is sourcing: do not commit a new production build without qualifying a drop-in alternative such as EPM9560RC304-15 and confirming date codes and authenticity from independent distributors. Also verify that the MAX+PLUS II development toolchain supports your target device and that the JTAG ISP chain is intact before programming. Because MAX 9000 timing is deterministic, do not assume a faster speed grade is automatically safe: re-run static timing analysis after any speed-grade substitution.
Compliance Information
No compliance data was present in the verified web data for the EPM9560RCRC304-15. As an obsolete Altera MAX 9000 device, RoHS/REACH/lead-free status must be confirmed from the specific date-code lot's certificate of conformance.
