EPM9560RI208-10N vs EPM9320RI208-20N Comparison

Detailed side-by-side comparison of EPM9560RI208-10N by Altera and EPM9320RI208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RI208-10N EPM9320RI208-20N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $61.75 $0.00
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Architecture CMOS EEPROM-based Multiple Array MatriX (MAX) β€”
Usable Gates 12,000 β€”
Macro Cells 560 β€”
Register Bits 12,160 β€”
User I/Os 212 β€”
Pin-to-Pin Delay 10 ns (speed grade -10) β€”
Maximum Frequency 100 MHz to 125 MHz β€”
Supply Voltage 5 V β€”
Package 208-pin RQFP (PQFP) 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature -40C to +85C (Industrial grade, "RI" suffix) β€”
Programming Method In-system via IEEE 1149.1 (JTAG) β€”
MSL Level 3 (168 Hours) β€”
RoHS Status ROHS3 Compliant (per fpgalink) [DATA_NEEDED: RoHS status]
Configuration Memory On-chip EEPROM (non-volatile) EEPROM (non-volatile)
Device Family β€” MAX 9000 (EPM9320)
Logic Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells β€” 320
Flip-Flops β€” 484
Propagation Delay (tPD) β€” 20 ns
Supply Voltage (VCC) β€” 5.0 V
I/O Voltage Tolerance β€” 3.3 V or 5 V configurable
Package Lead Pitch β€” 0.500 mm
Number of Terminals β€” 208
Operating Temperature Range β€” -40C to +85C (Industrial)
In-System Programmability β€” Yes, 5.0 V ISP via JTAG
JTAG Interface β€” IEEE Std. 1149.1 compliant
Dedicated Input Pins β€” 4 (low-skew global distribution)
Minimum DC Input on I/O Pins β€” -0.5 V
Minimum DC Input on Dedicated Inputs β€” -0.3 V
Input Undershoot/ Overshoot β€” -2.0 V / 7.0 V for <20 ns (no-load)
Mounting Type β€” Surface Mount

Datasheets & Resources

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