EPM9560WC208-15 vs EPM9560WC208 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560WC208-15 sa pamamagitan ng Altera at EPM9560WC208 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560WC208-15 | EPM9560WC208 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EE Programmable Logic Device (CPLD) |
| Technology | CMOS | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Flip-Flops | 772 | 772 |
| User I/O Pins (max) | 149 | — |
| Maksimum na Taktiko ng Oras | 117.6 MHz | 117.6 MHz |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | — |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Packhaging | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | 0.50 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | IEEE 1149.1 JTAG |
| Tindminan RoHS | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS compliance] |
| Maximum User I/O | — | 149 |
| Propagation Delay (tpd, -15 grade) | — | 16.6 ns |
| Volte ng Pagbibigay | — | 3.3 V or 5 V |
| Process Technology | — | CMOS, electrically erasable |
| Configuration Memory | — | Non-volatile EE (instant-on) |
| Hot Socketing Support | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |