EPM9560WC208-20 vs EPM9560WC208 Comparison

Detailed side-by-side comparison of EPM9560WC208-20 by Altera and EPM9560WC208 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560WC208-20

EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera

EPM9560WC208-20 Obsolete

Specification Comparison

Parameter EPM9560WC208-20 EPM9560WC208
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $25.80 $125.00
Family MAX 9000 MAX 9000
Device Type CPLD (EPLD) EE Programmable Logic Device (CPLD)
Macrocells 560 560
Logic Array Blocks (LABs) 35 35
User I/O Pins 149 β€”
Maximum Propagation Delay (tPD) 23.6 ns β€”
Package PQFP-208 (RQFP/WQFP) 208-pin CQFP (Ceramic Quad Flat Pack)
Process Technology CMOS, EEPROM-based CMOS, electrically erasable
Supply Voltage (VCCINT) 5 V (typical, see datasheet) β€”
I/O Voltage (VCCIO) 3.3 V or 5 V (multi-voltage I/O) β€”
In-System Programmability Yes, JTAG BST (IEEE 1149.1) β€”
Pin/Package Suffix W = power PQFP; -20 = 23.6 ns speed grade β€”
Operating Temperature Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] β€”
Mounting Type Surface Mount Surface Mount
RoHS Status Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED] β€”
Halogen-Free [DATA_NEEDED] β€”
MSL Level [DATA_NEEDED] [DATA_NEEDED: MSL level]
Flip-Flops β€” 772
Maximum User I/O β€” 149
Maximum Clock Frequency β€” 117.6 MHz
Propagation Delay (tpd, -15 grade) β€” 16.6 ns
Supply Voltage β€” 3.3 V or 5 V
Terminal Pitch β€” 0.50 mm
Programming Interface β€” IEEE 1149.1 JTAG
Configuration Memory β€” Non-volatile EE (instant-on)
Hot Socketing Support β€” Yes

Datasheets & Resources

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