EPM9560WC208-20 vs EPM9560WC208 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560WC208-20 disebabkan oleh Altera dan EPM9560WC208 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM9560WC208-20 EPM9560WC208
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 9000 MAX 9000
Device Type CPLD (EPLD) EE Programmable Logic Device (CPLD)
Macrocells 560 560
Logic Array Blocks (LABs) 35 35
User I/O Pins 149 —
Maximum Propagation Delay (tPD) 23.6 ns —
Kemasan PQFP-208 (RQFP/WQFP) 208-pin CQFP (Ceramic Quad Flat Pack)
Process Technology CMOS, EEPROM-based CMOS, electrically erasable
Supply Voltage (VCCINT) 5 V (typical, see datasheet) —
I/O Voltage (VCCIO) 3.3 V or 5 V (multi-voltage I/O) —
In-System Programmability Yes, JTAG BST (IEEE 1149.1) —
Pin/Package Suffix W = power PQFP; -20 = 23.6 ns speed grade —
Suhu Operasi Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] —
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED] —
Boson Bebas [DATA_NEEDED] —
Aras MSL [DATA_NEEDED] [DATA_NEEDED: MSL level]
Flip-Flops — 772
Maximum User I/O — 149
Frekuensi Klock Maksimum — 117.6 MHz
Propagation Delay (tpd, -15 grade) — 16.6 ns
Tegangan Pemberi Arus — 3.3 V or 5 V
Terminal Pitch — 0.50 mm
Programming Interface — IEEE 1149.1 JTAG
Configuration Memory — Non-volatile EE (instant-on)
Hot Socketing Support — Yes

Laporan Datasheet & Sumber

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