EPM9560WC208 vs EPM9560RC208-10 Comparison
Detailed side-by-side comparison of EPM9560WC208 by Altera and EPM9560RC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208 | EPM9560RC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 16 |
| Flip-Flops | 772 | — |
| Maximum User I/O | 149 | — |
| Maximum Clock Frequency | 117.6 MHz | — |
| Propagation Delay (tpd, -15 grade) | 16.6 ns | — |
| Supply Voltage | 3.3 V or 5 V | — |
| Process Technology | CMOS, electrically erasable | 0.30 µm CMOS EEPROM |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (Plastic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EE (instant-on) | EEPROM (in-system programmable via JTAG) |
| Hot Socketing Support | Yes | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in retrieved distributor listings] |
| Maximum User I/O Pins | — | 212 (208-pin package variant) |
| Usable Gates | — | 12,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: internal toggle frequency in MHz] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Standards Supported | — | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) |
| Operating Temperature | — | 0C to +70C (commercial) |
| Lead-Free | — | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] |
| Programmability | — | JTAG (IEEE 1149.1) in-system programming |