EP1810JC-35 vs EP1810JC-45 Vergleich
Detaillierter Direktvergleich von EP1810JC-35 von Intel und EP1810JC-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JC-35 | EP1810JC-45 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,48 | $21,10 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns |
| Maximale Taktfrequenz | [DATA_NEEDED: fmax for this speed grade] | 33.3 MHz |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | 5.25 V |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Betriebstemperaturbereich | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | Commercial |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS-Status | Compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Montageart | Surface Mount (J-Lead) | Surface Mount |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Technology | — | CMOS, UV-erasable |
| Gehäuse | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Pin-Anzahl | — | 68 |
| Package Code | — | QCCJ |