EP1810JC-35 vs EP1810JC-45 对比
详细并排对比 EP1810JC-35 出自 Intel 和 EP1810JC-45 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-35 | EP1810JC-45 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $5.48 | $21.10 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns |
| 最大时钟频率 | [DATA_NEEDED: fmax for this speed grade] | 33.3 MHz |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | 5.25 V |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 工作温度范围 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | Commercial |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 状态 | Compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| 安装类型 | Surface Mount (J-Lead) | Surface Mount |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Technology | — | CMOS, UV-erasable |
| 封装 | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| 引脚数量 | — | 68 |
| Package Code | — | QCCJ |