EP910JC-30 vs EP910PI-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910JC-30 sa pamamagitan ng Intel at EP910PI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910JC-30 EP910PI-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (MAX-style) —
Propagation Delay (tpd) 30 ns —
Maximum Internal Frequency (Fmax) 33.3 MHz —
Macrocells 24 24
Inputs 36 —
Product Terms 240 —
Outputs 10 dedicated —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM, UV-erasable CMOS EPROM (UV-erasable windowed variants available)
Packhaging 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) PDIP-40 (PI suffix)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Supply Current (Icc) [DATA_NEEDED: Icc typical / maximum] —
Uri ng Pagpapasok Surface Mount (socket-mountable) Through-Hole
Tindminan RoHS [DATA_NEEDED: RoHS compliance] unknown
Logic Blocks 24 macrocells (AND/OR array architecture) —
Device Family — Altera Classic EPLD Family
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5 V (+/- 5%)
Configuration Method — Non-volatile EPROM (no boot PROM required)
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

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