EPC2C20 vs EPC2-TC32 Vergleich
Detaillierter Direktvergleich von EPC2C20 von Altera und EPC2-TC32 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC2-TC32 - 1.6Mb ISP Configuration PROM | Altera | TQFP-32
EPC2-TC32 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC2C20 | EPC2-TC32 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $15,90 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | Serial (FPP/MSD via FPGA master/slave) |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Gehäuse | [DATA_NEEDED: package] | 32-pin TQFP (7x7 mm) |
| Pin-Anzahl | [DATA_NEEDED: pin count] | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Speichertyp | — | EPROM (OTP/UV-erasable configuration PROM) |
| Speichergröße | — | 1.6 Mbit |
| Schnittstellentyp | — | Serial |
| Speicherorganisation | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Versorgungsspannung | — | 3.3 V |
| Montageart | — | Surface Mount |
| Supported FPGA Families | — | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| MSL-Level | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |