EPC2C20 vs EPC2-TC32 Comparaison
Comparaison détaillée côte à côte de EPC2C20 par Altera et EPC2-TC32 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2C20 | EPC2-TC32 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $15,90 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | Serial (FPP/MSD via FPGA master/slave) |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Boîtier | [DATA_NEEDED: package] | 32-pin TQFP (7x7 mm) |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Type de mémoire | — | EPROM (OTP/UV-erasable configuration PROM) |
| Taille de mémoire | — | 1.6 Mbit |
| Type d'interface | — | Serial |
| Organisation de la mémoire | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Tension d'alimentation | — | 3.3 V |
| Type de montage | — | Surface Mount |
| Supported FPGA Families | — | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| Niveau MSL | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |