EPC2C20 vs EPC2-TC32 Comparación
Comparación detallada lado a lado de EPC2C20 por Altera y EPC2-TC32 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2C20 | EPC2-TC32 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | Activo | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $15,90 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | Serial (FPP/MSD via FPGA master/slave) |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Encapsulado | [DATA_NEEDED: package] | 32-pin TQFP (7x7 mm) |
| Recuento de pines | [DATA_NEEDED: pin count] | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Tipo de memoria | — | EPROM (OTP/UV-erasable configuration PROM) |
| Tamaño de memoria | — | 1.6 Mbit |
| Tipo de interfaz | — | Serial |
| Organización de memoria | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Tensión de alimentación | — | 3.3 V |
| Tipo de montaje | — | Surface Mount |
| Supported FPGA Families | — | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| Nivel MSL | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |