EPM5016DC-20 vs EPM5032DI-25 Vergleich

Detaillierter Direktvergleich von EPM5016DC-20 von Altera und EPM5032DI-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5016DC-20 EPM5032DI-25
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,50 $18,20
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable Programmable Logic Device) UV-erasable Programmable Logic Device (PLD)
Macrocells 16 32
Product Terms 160 320
Dedicated Inputs 7 7
I/O Pins 8 —
Propagation Delay (tPD) 20 ns 25 ns
Maximale Taktfrequenz 62.5 MHz —
Maximum Supply Voltage 5.25 V —
Nominal Supply Voltage 5.0 V —
Process Technology CMOS, UV-erasable CMOS
Architecture PAL-type macrocell with Programmable Interconnect Array (PIA) PAL-type, CMOS, AND-OR sum-of-products
Package Type 20-pin Ceramic DIP (Cerdip) with UV window —
Package Suffix Code DC = Ceramic DIP, Commercial —
Speed Grade -20 = 20 ns tPD —
Betriebstemperatur [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Programming Method UV erase + EPROM-style programming via Altera programming hardware —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Logic Gates — [DATA_NEEDED: equivalent gate count]
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Maximum Clock Frequency (fMAX) — 62.5 MHz
Versorgungsspannung — 5 V
Gehäuse — Ceramic DIP, windowed (UV-erasable)
Pin-Anzahl — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

Datenblätter & Ressourcen

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