EPM5016DC-20 vs EPM5032DI-25 Comparaison
Comparaison détaillée côte à côte de EPM5016DC-20 par Altera et EPM5032DI-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5016DC-20 | EPM5032DI-25 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,50 | $18,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | 16 | 32 |
| Product Terms | 160 | 320 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Fréquence d'horloge maximale | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | CMOS |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type, CMOS, AND-OR sum-of-products |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Tension d'alimentation | — | 5 V |
| Boîtier | — | Ceramic DIP, windowed (UV-erasable) |
| Nombre de broches | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |