EPM5016DC-20 vs EPM5032DI-25 비교
다음의 상세 나란히 비교: EPM5016DC-20 제조: Altera 및 EPM5032DI-25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5016DC-20 | EPM5032DI-25 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.50 | $18.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | 16 | 32 |
| Product Terms | 160 | 320 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| 최대 클록 주파수 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | CMOS |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type, CMOS, AND-OR sum-of-products |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| 공급 전압 | — | 5 V |
| 패키지 | — | Ceramic DIP, windowed (UV-erasable) |
| 핀 수 | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |