EPM5016DC-20 vs EPM5032DI-25 对比
详细并排对比 EPM5016DC-20 出自 Altera 和 EPM5032DI-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5016DC-20 | EPM5032DI-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.50 | $18.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | 16 | 32 |
| Product Terms | 160 | 320 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| 最大时钟频率 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | CMOS |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type, CMOS, AND-OR sum-of-products |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| 电源电压 | — | 5 V |
| 封装 | — | Ceramic DIP, windowed (UV-erasable) |
| 引脚数量 | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |