EPM5032DM883B vs EPM5032DC20 Vergleich

Detaillierter Direktvergleich von EPM5032DM883B von Altera und EPM5032DC20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5032DM883B EPM5032DC20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $64,50 $8,20
Family MAX 5000 (Classic EPLD) —
Macrocells 32 32
Logic Elements 32 macrocells (MAX architecture) —
Technology UV-erasable EPROM cell —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns] 20 ns
Maximum Counter Frequency (fCNT) [DATA_NEEDED: fCNT in MHz] —
Supply Voltage (VCC) 5 V (nominal, TTL-compatible I/O) 5 V (4.75 V to 5.25 V)
Betriebstemperatur MILITARY (per /883B screen) [DATA_NEEDED: operating temperature range]
MIL-STD-883 Screening Class B (DM/883B) —
Package Type WDIP-28 (ceramic DIP with quartz window) —
Pin-Anzahl 28 —
Montageart Through-Hole Through-Hole (DIP)
Terminal Form Through-Hole —
Package Shape RECTANGULAR —
Programming Method Programmer + UV erase —
RoHS-Status [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] [DATA_NEEDED: RoHS compliance]
Device Family — MAX 5000
Product Type — UV-erasable PLD (CPLD class)
Usable Gates — 600
Maximum Frequency (Fmax) — 71.4 MHz
Dedicated Inputs — 7
I/O Pins — 16 (bidirectional)
Total Inputs (max) — 24
Output Macrocells — 16
Clock Inputs — 1 (global)
Architecture — PAL-type with Programmable Interconnect Array (PIA)
Process Technology — CMOS
Gehäuse — 20-pin Ceramic DIP (DC) with UV window

Datenblätter & Ressourcen

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