EPM5032DM883B vs EPM5032DC20 对比

详细并排对比 EPM5032DM883B 出自 Altera 和 EPM5032DC20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032DM883B EPM5032DC20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $64.50 $8.20
Family MAX 5000 (Classic EPLD) —
Macrocells 32 32
Logic Elements 32 macrocells (MAX architecture) —
Technology UV-erasable EPROM cell —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns] 20 ns
Maximum Counter Frequency (fCNT) [DATA_NEEDED: fCNT in MHz] —
Supply Voltage (VCC) 5 V (nominal, TTL-compatible I/O) 5 V (4.75 V to 5.25 V)
工作温度 MILITARY (per /883B screen) [DATA_NEEDED: operating temperature range]
MIL-STD-883 Screening Class B (DM/883B) —
Package Type WDIP-28 (ceramic DIP with quartz window) —
引脚数量 28 —
安装类型 Through-Hole Through-Hole (DIP)
Terminal Form Through-Hole —
Package Shape RECTANGULAR —
Programming Method Programmer + UV erase —
RoHS 状态 [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] [DATA_NEEDED: RoHS compliance]
Device Family — MAX 5000
Product Type — UV-erasable PLD (CPLD class)
Usable Gates — 600
Maximum Frequency (Fmax) — 71.4 MHz
Dedicated Inputs — 7
I/O Pins — 16 (bidirectional)
Total Inputs (max) — 24
Output Macrocells — 16
Clock Inputs — 1 (global)
Architecture — PAL-type with Programmable Interconnect Array (PIA)
Process Technology — CMOS
封装 — 20-pin Ceramic DIP (DC) with UV window

数据手册与资源

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