EPM51929C vs EPM5192-1LC Vergleich

Detaillierter Direktvergleich von EPM51929C von Intel und EPM5192-1LC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM51929C EPM5192-1LC
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,40 $19,40
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multi-array matrix (PAL-based macrocells) —
Logic Density [DATA_NEEDED: usable gates] —
Number of Macrocells [DATA_NEEDED: macrocell count] —
Anzahl der Pins [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map —
Betriebstemperatur Commercial (0C to +70C) 0C to +70C (commercial)
Versorgungsspannung [DATA_NEEDED: VCC range] 5 V
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
Montageart Surface Mount or Through-Hole (package dependent) Surface Mount
RoHS-Status unknown Non-compliant (ceramic windowless package, lead-bearing termination)
Lead-Free unknown —
MSL-Level [DATA_NEEDED] —
Family — MAX 5000
Usable Gates — 3,750
Macrocells — 192
Logic Array Blocks (LABs) — 4
User I/O Pins — 64
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tpd) — [DATA_NEEDED: -1 speed grade tpd in ns]
Process Technology — UV EPROM, erasable windowless
Programmable Interconnect — PIA (Programmable Interconnect Array)
JTAG Boundary Scan — IEEE 1149.1 compliant
Gehäuse — 64-pin Ceramic J-Lead Chip Carrier (LC)

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