EPM51929C vs EPM5192-1LC 对比

详细并排对比 EPM51929C 出自 Intel 和 EPM5192-1LC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM51929C EPM5192-1LC
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $9.40 $19.40
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multi-array matrix (PAL-based macrocells) —
Logic Density [DATA_NEEDED: usable gates] —
Number of Macrocells [DATA_NEEDED: macrocell count] —
引脚数 [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map —
工作温度 Commercial (0C to +70C) 0C to +70C (commercial)
电源电压 [DATA_NEEDED: VCC range] 5 V
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
安装类型 Surface Mount or Through-Hole (package dependent) Surface Mount
RoHS 状态 unknown Non-compliant (ceramic windowless package, lead-bearing termination)
Lead-Free unknown —
MSL 等级 [DATA_NEEDED] —
Family — MAX 5000
Usable Gates — 3,750
Macrocells — 192
Logic Array Blocks (LABs) — 4
User I/O Pins — 64
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tpd) — [DATA_NEEDED: -1 speed grade tpd in ns]
Process Technology — UV EPROM, erasable windowless
Programmable Interconnect — PIA (Programmable Interconnect Array)
JTAG Boundary Scan — IEEE 1149.1 compliant
封装 — 64-pin Ceramic J-Lead Chip Carrier (LC)

数据手册与资源

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