EPM51929C vs EPM5192-1LC 비교

다음의 상세 나란히 비교: EPM51929C 제조: Intel 및 EPM5192-1LC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM51929C EPM5192-1LC
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $9.40 $19.40
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multi-array matrix (PAL-based macrocells) —
Logic Density [DATA_NEEDED: usable gates] —
Number of Macrocells [DATA_NEEDED: macrocell count] —
핀 수 [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map —
동작 온도 Commercial (0C to +70C) 0C to +70C (commercial)
공급 전압 [DATA_NEEDED: VCC range] 5 V
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
실장 유형 Surface Mount or Through-Hole (package dependent) Surface Mount
RoHS 상태 unknown Non-compliant (ceramic windowless package, lead-bearing termination)
Lead-Free unknown —
MSL 레벨 [DATA_NEEDED] —
Family — MAX 5000
Usable Gates — 3,750
Macrocells — 192
Logic Array Blocks (LABs) — 4
User I/O Pins — 64
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tpd) — [DATA_NEEDED: -1 speed grade tpd in ns]
Process Technology — UV EPROM, erasable windowless
Programmable Interconnect — PIA (Programmable Interconnect Array)
JTAG Boundary Scan — IEEE 1149.1 compliant
패키지 — 64-pin Ceramic J-Lead Chip Carrier (LC)

데이터시트 & 자료

모든 제품 보기 BOM 생성 견적 요청