EPM51929C vs EPM5192-1LC Comparaison
Comparaison détaillée côte à côte de EPM51929C par Intel et EPM5192-1LC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM51929C | EPM5192-1LC |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,40 | $19,40 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multi-array matrix (PAL-based macrocells) | — |
| Logic Density | [DATA_NEEDED: usable gates] | — |
| Number of Macrocells | [DATA_NEEDED: macrocell count] | — |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Package Type | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, JEDEC fuse map | — |
| Température de fonctionnement | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | 5 V |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fmax] | — |
| Type de montage | Surface Mount or Through-Hole (package dependent) | Surface Mount |
| Statut RoHS | unknown | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Lead-Free | unknown | — |
| Niveau MSL | [DATA_NEEDED] | — |
| Family | — | MAX 5000 |
| Usable Gates | — | 3,750 |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Process Technology | — | UV EPROM, erasable windowless |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Boîtier | — | 64-pin Ceramic J-Lead Chip Carrier (LC) |