MSC8251SVT1000B vs MSC8157TAG1000A Vergleich
Detaillierter Direktvergleich von MSC8251SVT1000B von NXP Semiconductors und MSC8157TAG1000A von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
MSC8157TAG1000A - 6-Core SC3850 DSP, 1GHz, MAPLE-B2 | NXP
MSC8157TAG1000A ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | MSC8251SVT1000B | MSC8157TAG1000A |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | DSP | DSP |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $65,00 | $178,00 |
| Manufacturer | NXP Semiconductors (formerly Freescale Semiconductor) | — |
| Core Architecture | SC3850 StarCore, single core | — |
| Core Revision | StarCore R2.1 | — |
| Maximum Core Clock | 1 GHz | — |
| MIPS | [DATA_NEEDED: MIPS rating for 1 GHz SC3850] | — |
| L1 Instruction Cache | 32 KB | 32 KB per core |
| L1 Data Cache | 32 KB | 32 KB per core |
| L2 Unified Cache | 512 KB (configurable, SRAM or MAP) | — |
| On-Chip RAM | 576 KB | — |
| Internal ROM | 96 KB | — |
| TDM Interfaces | 4 modules, up to 62.5 Mbps each, with H.110/H-MVIP support | — |
| Ethernet MAC | Yes (integrated) | — |
| PCI Express | Yes (integrated controller) | — |
| Serial RapidIO | Yes (SERDES-based) | — |
| DMA Controller | Multi-channel DMA | — |
| Package Type | FCBGA (Flip-Chip Ball Grid Array) | — |
| Package Pin Count | 783 balls | — |
| Package Dimensions | 29 mm x 29 mm | — |
| Montageart | Surface Mount | — |
| Lead-Free / Halogen-Free | Yes (lead-free, halogen-free package) | — |
| RoHS-Status | Compliant | [DATA_NEEDED] |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | -40C to +105C |
| Device Type | — | Six-core Digital Signal Processor (DSP) |
| DSP Architecture | — | StarCore SC3850 (6x cores) |
| Core Frequency | — | 1 GHz per core |
| Unified L2 Cache | — | 512 KB (configurable as M2 in 64 KB increments) |
| Accelerator | — | MAPLE-B2 baseband accelerator |
| Memory Controller | — | Dual-channel DDR2/DDR3 with ECC |
| High-Speed Serial I/O | — | 2x SRIO, 2x PCIe, 2x GbE, 2x CIPRI |
| Gehäuse | — | 783-FCPBGA (29x29 mm) |
| Ball Pitch | — | 1.0 mm |
| Versorgungsspannung | — | [DATA_NEEDED: core/IO voltage] |
| MMU | — | Yes |
| Interrupt Controller | — | EPIC (Extended Programmable Interrupt Controller) |
| Timers | — | 2x 32-bit general-purpose per core |
| MSL-Level | — | [DATA_NEEDED] |