SN65LVDS105PWRG4 vs SN65LVDS105PWR Vergleich
Detaillierter Direktvergleich von SN65LVDS105PWRG4 von Texas Instruments und SN65LVDS105PWR von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Texas Instruments
SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWRG4 ✗ AbgekündigtSpezifikationsvergleich
| Parameter | SN65LVDS105PWRG4 | SN65LVDS105PWR |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | Clock & Timing | Clock & Timing |
| Lebenszyklusstatus | Ende des Lebenszyklus | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $1,28 |
| Funktion | 1 LVTTL to 4 LVDS clock fanout buffer / repeater | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Configuration | 1 x 1:4 Channel | — |
| Input Type | LVTTL | LVTTL (single-ended) |
| Ausgangstyp | LVDS (4 differential pairs) | LVDS (differential), 4 pairs |
| Max Data Rate | 400 Mbps | — |
| Supply Voltage Range | 3 V to 3.6 V | — |
| Typical Propagation Delay | 2.2 ns | — |
| Typical LVDS Output Voltage | 285 mV into 100 ohm load | — |
| Signaling Standard | ANSI EIA/TIA-644 (LVDS) | — |
| Bus-Terminal ESD Rating | Exceeds 12 kV | — |
| Gehäuse | TSSOP-16 (PW), 5 mm x 6.4 mm | 16-TSSOP (PW) |
| Montageart | Surface Mount | Surface Mount |
| Packaging | Tape & Reel (PWR suffix) | — |
| Kategorie | Interface - Signal Buffers, Repeaters, Splitters | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Lebenszyklusstatus | Discontinued at Digi-Key | — |
| Datenrate | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Versorgungsspannung | — | 3 V to 3.6 V (typical 3.3 V) |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Kanäle | — | 1 x 1:4 |
| Technology | — | LVDS differential signaling |
| Ruhestrom | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |