SN65LVDS105PWRG4 vs SN65LVDS105PWR Comparação

Comparação detalhada lado a lado de SN65LVDS105PWRG4 por Texas Instruments e SN65LVDS105PWR por Texas Instruments. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Texas Instruments
SN65LVDS105PWRG4 SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWRG4 ✗ Fim de vida
Texas Instruments
SN65LVDS105PWR SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR ✓ Ativo

Comparação de especificações

Parâmetro SN65LVDS105PWRG4 SN65LVDS105PWR
Marca Texas Instruments Texas Instruments
Categoria Clock & Timing Clock & Timing
Status do ciclo de vida Fim de vida Ativo
Status do estoque In Stock In Stock
Preço unitário (USD) $0,00 $1,28
Função 1 LVTTL to 4 LVDS clock fanout buffer / repeater 1 LVTTL input to 4 LVDS output repeater / fanout buffer
Configuration 1 x 1:4 Channel —
Input Type LVTTL LVTTL (single-ended)
Tipo de saída LVDS (4 differential pairs) LVDS (differential), 4 pairs
Max Data Rate 400 Mbps —
Supply Voltage Range 3 V to 3.6 V —
Typical Propagation Delay 2.2 ns —
Typical LVDS Output Voltage 285 mV into 100 ohm load —
Signaling Standard ANSI EIA/TIA-644 (LVDS) —
Bus-Terminal ESD Rating Exceeds 12 kV —
Encapsulamento TSSOP-16 (PW), 5 mm x 6.4 mm 16-TSSOP (PW)
Tipo de montagem Surface Mount Surface Mount
Packaging Tape & Reel (PWR suffix) —
Categoria Interface - Signal Buffers, Repeaters, Splitters Signal Buffers, Repeaters, Splitters - Clock Buffer
Status RoHS [DATA_NEEDED: RoHS status] —
Temperatura de operação [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Status do ciclo de vida Discontinued at Digi-Key —
Taxa de dados — 400 Mbps
Max Clock Frequency — 400 MHz
Tensão de alimentação — 3 V to 3.6 V (typical 3.3 V)
Output Voltage (typical) — 350 mV into 100 ohm load
Standard Compliance — ANSI EIA/TIA-644 LVDS
Canais — 1 x 1:4
Technology — LVDS differential signaling
Corrente de repouso — [DATA_NEEDED: quiescent current]
Input Rise/Fall Time Note — TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance

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