SN65LVDS105PWRG4 vs SN65LVDS105PWR Comparación
Comparación detallada lado a lado de SN65LVDS105PWRG4 por Texas Instruments y SN65LVDS105PWR por Texas Instruments. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Texas Instruments
SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWRG4 ✗ Fin de vidaTexas Instruments
SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWR ✓ ActivoComparación de especificaciones
| Parámetro | SN65LVDS105PWRG4 | SN65LVDS105PWR |
|---|---|---|
| Marca | Texas Instruments | Texas Instruments |
| Categoría | Clock & Timing | Clock & Timing |
| Estado del ciclo de vida | Fin de vida | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $1,28 |
| Función | 1 LVTTL to 4 LVDS clock fanout buffer / repeater | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Configuration | 1 x 1:4 Channel | — |
| Input Type | LVTTL | LVTTL (single-ended) |
| Tipo de salida | LVDS (4 differential pairs) | LVDS (differential), 4 pairs |
| Max Data Rate | 400 Mbps | — |
| Supply Voltage Range | 3 V to 3.6 V | — |
| Typical Propagation Delay | 2.2 ns | — |
| Typical LVDS Output Voltage | 285 mV into 100 ohm load | — |
| Signaling Standard | ANSI EIA/TIA-644 (LVDS) | — |
| Bus-Terminal ESD Rating | Exceeds 12 kV | — |
| Encapsulado | TSSOP-16 (PW), 5 mm x 6.4 mm | 16-TSSOP (PW) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Packaging | Tape & Reel (PWR suffix) | — |
| Categoría | Interface - Signal Buffers, Repeaters, Splitters | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Estado del ciclo de vida | Discontinued at Digi-Key | — |
| Velocidad de datos | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Tensión de alimentación | — | 3 V to 3.6 V (typical 3.3 V) |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Canales | — | 1 x 1:4 |
| Technology | — | LVDS differential signaling |
| Corriente en reposo | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |