EPM3512AQC208-2 vs EPM3512AQC208-7 Comparación
Comparación detallada lado a lado de EPM3512AQC208-2 por Altera y EPM3512AQC208-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndComparación de especificaciones
| Parámetro | EPM3512AQC208-2 | EPM3512AQC208-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,75 | $41,72 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| User I/O Pins | 172 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Speed Grade | -2 | — |
| Encapsulado | PQFP-208 (QC) | 208-Pin PQFP (FQFP, gull-wing) |
| Supply Voltage (Core) | 3.3 V | — |
| Output Drive Voltage | 2.5 V / 3.3 V programmable | — |
| Input Voltage Tolerance | 2.5 V / 3.3 V / 5.0 V | — |
| Process Technology | 0.30 µm EEPROM | CMOS EEPROM, 0.30 um |
| Program/Erase Endurance | 100 cycles (typical) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| User I/O Banks | 4 | — |
| Rango de temperatura de funcionamiento | Commercial (0C to +70C) | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | Non-compliant (legacy PQFP) | Compliant |
| Lead-Free | No (SnPb lead finish) | Yes |
| Security Bit | Yes (programmable) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 116.3 MHz |
| User I/Os | — | 172 |
| Logic Elements / LEs | — | N/A (CPLD macrocell architecture) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standards Supported | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Temperatura de funcionamiento | — | 0 C to +70 C (commercial) |
| Programming | — | In-System Programmable via JTAG (IEEE Std. 1532) |